In many types of systems, access to a resource must be allocated between competitors for that resource. An example is the allocation of access to a memory that stores information received from a plurality of sources. A memory interface is often employed to control the access from the sources to the memory. These sources may be connected to the memory interface by a plurality of different buses, for example.
One type of system in which there is an allocation of access to a memory is a network switch for a packet switched network. In such a network switch, the memory may be used to store data frames received at one port of the switch and are then forwarded to another port of the switch. The memory may also be used to store, at least temporarily, control information or configuration information. The different types of information to be stored in the memory may arrive via a number of different buses. A typical allocation scheme to allocate the access to the memory by the buses is a fixed slot time-division multiplex (TDM) scheme. In such a scheme, each source may be assigned one or more specified slots within a given time period to perform a transfer (either a read or a write) with the memory. Various provisions may be made for unused slots, such as re-assigning the slot to another resource for that time period. When the time period is over, the sources again will perform their transfers with the memory during their assigned time slots.
One concern facing designers of integrated circuits is the increasing speed demands placed on their designs. Once a circuit has been designed and manufactured, it is difficult to obtain higher speed performance from the integrated circuit. In the example of memory access, the operating frequency of the memory is a limiting factor. When the memory is formed as part of the network switch, and the operating frequency of the memory is fixed, then the number of slots that are available for transfers between the various sources and buses and the memory will be fixed for a given period of time, assuming a constant transfer amount. This fixes the amount of data that can be transferred to and from the memory within a given period of time. For example, if a memory operates at 80 MHz, and a transfer of 32 bytes of data requires 16 clock cycles to complete, then 4 such slots are available in a period of time of 0.8 microseconds to transfer 128 bytes of data. One way to transfer more data is to speed up the operating frequency of the entire integrated circuit. Simply speeding up the system has the tendency, however, of creating additional problems with the operation of the overall system. This design limitation hinders the ability of the circuit designer from providing an arrangement that can be tailored to provide access to a number of different sources in response to different system requirements.